1. Field of Invention
The invention relates to the field of integrated circuit memory devices. More particularly, the invention relates to apparatus and methods for testing memory cells in integrated circuit memory devices.
2. Discussion of Related Art
Memory embedded in microprocessors, such as static random-access memory (SRAM), can be susceptible to data storage errors. Microprocessors are often used in applications that require infrequent reads and writes of memory cells and flip-flops. In embedded and low power applications, for example, the microprocessor may be placed in a low-power mode of operation in which it suspends access to memory for a time span of anywhere from several seconds to hours or days. Unfortunately, manufacturing defects can cause data values stored in memory cells or flip-flops to change state over time (e.g., a stored logic-1 erroneously becomes a logic-0, or vice versa). Thus, device manufacturers and purchases often perform data retention tests on each microprocessor to test the ability of the memory to retain stored data for a desired period of time.
A typical SRAM cell is fabricated via standard integrated circuit methods. Because it is often desirable to provide the greatest possible amount of memory in the smallest possible circuit area, SRAM cells are often formed with minimal component dimensions. SRAM cells are thus susceptible to manufacturing defects. Such defects can lead to complete failure of a cell, or cause the cell to leak current and thus fail to retain stored data for a required period of time.
Unfortunately, manufacturing defects that cause data retention problems can be more difficult to detect than defects that prevent storage. Defects sometimes occur in the semiconductor and metal structures of an integrated circuit during such a manufacturing process. Such manufacturing defects can cause failures in the contacts in the SRAM cells or in the individual transistors in the SRAM cells. A symmetric defect impairs the performance of both of the cross-coupled devices of the cell. A defective contact in a power supply line, which normally supplies power to the entire memory cell, is considered a symmetric defect since both cross coupled devices are left without power. In contrast, an asymmetric defect normally impairs only one of the cross-coupled devices. A defective pull-up in one inverter is an example of an asymmetric defect.
Weak cells can be identified by observing the behavior of cells over a period of time. This approach can be unacceptably time consuming, and can lead to uncertain outcomes because different types of defects can cause a cell to retain data for different lengths of time. Another approach is to test more devices simultaneously. This solution, however, can require the use of greater numbers of costly test instruments. A third approach is to add to each column of memory cells an on-chip weak-write test circuit. This solution, however, can add substantial amounts of circuitry to a convention SRAM design.